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MC14070B, MC14077B CMOS SSI
Quad Exclusive "OR" and "NOR" Gates
The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired.
Features
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14 PDIP-14 P SUFFIX CASE 646 1 MC140xxBCP AWLYYWWG
* Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-Power TTL Loads or One Low-Power * * * *
Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs MC14070B - Replacement for CD4030B and CD4070B Types MC14077B - Replacement for CD4077B Type Pb-Free Packages are Available
14 SOIC-14 D SUFFIX CASE 751A 1 140xxBG AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C xx A WL, L YY, Y WW, W G SOEIAJ-14 F SUFFIX CASE 965 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 14 MC140xxB ALYWG
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 7
1
Publication Order Number: MC14070B/D
MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14070B QUAD Exclusive OR Gate 1 2 5 6 8 9 12 13 3 4 10 11
MC14077B QUAD Exclusive NOR Gate 1 2 5 6 8 9 12 13 3 4 10 11
VDD = PIN 14 VSS = PIN 7 (BOTH DEVICES)
20 ns VDD IDD Vin * CL Vin 90% 50% 10%
20 ns VDD VSS
1/f 50% DUTY CYCLE *Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
VDD PULSE GENERATOR * # VSS CL
20 ns INPUT tPHL OUTPUT tTHL 90% 50% 10% 90% 50% 10%
20 ns VDD VSS VOH VOL
tPLH
*Inverted output on MC14077B only. #Connect unused input to VDD for MC14070B, to VSS for MC14077B.
tTLH
Figure 2. Switching Time Test Circuit and Waveforms
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MC14070B, MC14077B
ORDERING INFORMATION
Device MC14070BCP MC14070BCPG MC14070BD MC14070BDG MC14070BDR2 MC14070BDR2G MC14070BFEL MC14070BFELG MC14077BCP MC14077BCPG MC14077BD MC14077BDG MC14077BDR2 MC14077BDR2G MC14077BFEL MC14077BFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail 2000 / Tape & Reel 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Propagation Delay Times (Note 3) (CL = 50 pF) tPLH, tPHL = (0.90 ns/pF) CL + 130 ns tPLH, tPHL = (0.36 ns/pF) CL + 57 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns Output Rise and Fall Times (Note 3) (CL = 50 pF) tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.60 ns/pF) CL + 20 ns tTLH, tTHL = (0.40 ns/pF) CL + 20 ns Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Characteristic "0" Level "0" Level "1" Level "1" Level Source Sink Symbol tPLH, tPHL tTLH, tTHL VOH VOL IOH VIH IDD IOL Cin VIL Iin IT
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk
where: IT is in mH (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002.
MC14070B, MC14077B
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
-
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 - - - - - - - - - - - - - - - - - - 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 1.5 3.0 4.0 -- - - - - - - - - - - - - - - - - - - - - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 IT = (0.3 mA/kHz) f + IDD IT = (0.6 mA/kHz) f + IDD IT = (0.9 mA/kHz) f + IDD - - - - - - - - - - - - - - - - - 0.00001 Typ (Note 2) 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 175 75 55 100 50 40 5.0 5.0 10 15 0 0 0 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 350 150 110 200 100 80 7.5 1.5 3.0 4.0 - - - - - - - - - - - - - - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 - - - - - - - - - - - - - - - - - 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.5 3.0 4.0 - - - - - - - - - - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF ns ns
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MC14070B, MC14077B
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC14070B, MC14077B
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC14070B, MC14077B
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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